1. Field of the Invention
This invention relates to metal semiconductor (MOS) field effect devices, and relates specifically to lateral double-diffused MOS (DMOS) field effect transistors.
2. Description of Related Art
Lateral double-diffused metal-oxide-semiconductor (lateral DMOS) transistors of the type having a lightly-doped drain (LDD) region (or "LDD lateral DMOS transistors") are often found in high-voltage integrated circuits. Among these LDD lateral DMOS devices, the self-isolated devices are especially desirable because of their relative ease of integration with low-voltage devices, which are often used to perform logic functions. The self-isolated devices are so described because, for N-channel devices, each transistor's N+ drain and source regions are separated from the N+ drain and source regions of other transistors by the reverse-biased PN-junction formed between each of these drain and source regions and the p-type substrate. Because of self-isolation, the self-isolated DMOS devices occupy less area and are relatively less costly than either the junction-isolated LDD lateral DMOS devices or the dielectric-isolated LDD lateral DMOS devices. An overview of the various types of LDD lateral DMOS devices discussed above can be found in "Power Integrated Circuits--A Brief Overview" by B. Baliga, IEEE Transactions on Electron Devices, Vol. ED-33, No. 12, December 1986, pp. 1936-9.
FIG. 1 is a cross section of an N-channel LDD lateral DMOS transistor 100 showing the double-diffused N+ source region 102 and P-body region 103. The P-body and source regions 103 and 102 are commonly connected by conductor 120, which connects the P-body region 108 via the P+ contact region 101. The drain of transistor 100 is formed by the N- LDD or drift region 122 and the N+ contact region 107. Transistor 100 is controlled by the voltage of gate 109, which is situated above the gate oxide 110 and enclosed by insulation layer 121. Optionally, a deep P+ region 104 can be formed to provide a good contact to the P- substrate 105. This deep P+ region 104 does not significantly impact the breakdown voltage of transistor 100, nor increases the parasitic capacitance associated with the transistor 100. An optional N-well 106 can also be formed to provide a "deep" drain region suitable for longer-drift high-voltage devices requiring a higher breakdown voltage. Transistor breakdown often occurs at the high electric field associated with the edge of the drift region 122 next to the N+ contact region 107 ("drain-edge"), if the drift region 122 is very lightly doped. Alternatively, breakdown is more likely to occur at the edge of the drift region 122 next to the gate 109 ("gate-edge"), if the drift region 122 is relatively more heavily doped. A higher dopant concentration in the drift region 122 reduces the on-resistance of the transistor 100, thereby allowing a higher saturation current. However, a breakdown at the surface near the gate-edge of drift region 122 may leave an amount of charge in the gate oxide 110, resulting in reliability problems and an unstable breakdown voltage.
FIG. 2 shows the electrical potential distribution when transistor 100 is in the "off" state. (In FIG. 2, the optional deep P+ region 104 and the optional N-well 106 are not shown). As shown in FIG. 2, high electric fields are indicated by the closely-spaced electrical equipotential lines "crowding" at the gate-edge of the drift region 122. The distribution of high electric fields at the gate edge lowers the breakdown voltage of transistor 100.
FIG. 3 illustrates one method in the prior art to relieve the crowding of electrical equipotential lines, and thereby increases the breakdown voltage of transistor 100. As shown in FIG. 3, a conductor 111, called a field plate, which is electrically connected either to the gate 109 or the source region 102, is situated above the gate-edge of the drift region 122. As shown in FIG. 3, the presence of the field plate 111 reduces the crowding of equipotentials at the gate-edge of the drift region 122 above the silicon surface, and hence lowers the electric field intensities at the gate-edge. The field plate 111 can be formed using polysilicon or metal. (When the field plate is electrically connected to the gate 109, the field plate is also known as the "gate plate"). However, there still remains high electric fields at the sidewalls (indicated by arrow A) of the N- drift region 122. Hence, the relief of electrical equipotential crowding using the gate plate approach is not satisfactory, particularly because reasonable and expected process variations in the doping concentration of the N- drift region 122 can exacerbate such field crowding.
Another method to increase breakdown voltage of a LDD lateral DMOS transistor is achieved by the reduced surface field (RESURF) technique, discussed in "High Voltage Thin Layer Devices (RESURF Devices)," by J. Appels et al, International Electron Device Meeting Technical Digest, December 1979, pp. 238-41. The RESURF technique provides the LDD lateral DMOS transistor in a lightly doped N- epitaxial layer on top of a P- substrate. In the RESURF technique, adjacent transistors are junction-isolated by P+ regions.
FIG. 4 shows a junction-isolated RESURF lateral DMOS transistor 200 having a field-shaping P+ buried layer 201. In FIG. 4, transistor 200 is fabricated in an N- epitaxial layer 206 formed on top of the P- substrate 205. Transistor 200 comprises the N+ source and drain regions 202 and 207, the P-body region 203, and gate 209, which is formed above a gate oxide layer 210 and enclosed in the insulator layer 221. The N+ source region 202 and the P-body region 203 are commonly connected by the metallization 220. In addition, transistor 200 is provided a field-shaping buried layer 201, which extends from the P+ isolation 204 and reaches horizontally underneath the gate region beyond the gate-edge of the drift region 222. In FIG. 4, in addition to the increased breakdown voltage due to the RESURF effects, the field-shaping P+ buried layer 201 enhances the breakdown voltage further by "uncrowding" the equipotential lines in the N- epitaxial layer 206 next to the gate region underneath 209. A similar transistor is disclosed in U.S. Pat. No. 4,300,150, entitled "lateral Double-diffused MOS transistor Device," by S. Colak, filed Jun. 16, 1980 and issued Nov. 10, 1981.
While RESURF lateral DMOS transistor 200 of FIG. 4 has its breakdown voltage enhanced, due to both the use of the RESURF technique and the field-shaping P+ buried layer 201, RESURF lateral DMOS transistor 200 is expensive from the packing density stand point because additional area is required by the P+ isolation region 204. In addition, the P+ isolation region 204 must be appropriately shaped, as shown in FIG. 4, to short the emitter-to-base junction of the high-gain parasitic vertical NPN transistor formed by the N+ source region 202, the P-body region 203, and the epitaxial region 206. Shorting the emitter-to-base junction prevents a phenomenon known as "common-emitter base-open breakdown voltage snap-back" ("BV.sub.CEO snapback"), which can destroy the device. In fabricating the P+ isolation region 204, care must be taken to ensure that the P+ diffusion penetrates the N- epitaxial layer into the P- substrate to ensure complete isolation.
Further, the P-body region 203 of RESURF lateral DMOS transistor 200 of FIG. 4 forms a reversed-bias junction with the N- epitaxial layer 206. Such reversed-biased junction increases the likelihood of punchthrough (barrier lowering) breakdown degradation in RESURF lateral DMOS transistor 200. As a result, the ability to integrate other bipolar or high voltage devices may be restricted by design considerations of the RESURF lateral DMOS transistor.
Therefore, a self-isolated LDD lateral DMOS transistor having reduced peak electric field at the gate-edge of the drift region is highly desirable. Such transistor would allow a higher dopant concentration in the drift region without reliability or breakdown voltage degradation. Further, such self-isolated LDD lateral DMOS transistor provides the breakdown voltage and reliability characteristics without incurring the area penalty of the P+ isolation in a RESURF type lateral DMOS transistor, and allows the designer further freedom to select and use thicker epitaxial layers for other purposes, such as for providing a vertical NPN transistor.